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S.NoProject CodeProject Title
VLSI Project TitleS
1VLSI18NXT01Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
2VLSI18NXT02A Simple Yet Efficient Accuracy-Configurable Adder Design
3VLSI18NXT03Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption
4VLSI18NXT04Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers
5VLSI18NXT05An Efficient Fault-Tolerance Design for Integer Parallel Matrix–Vector Multiplications
6VLSI18NXT06Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation
7VLSI18NXT07A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies
8VLSI18NXT08FIR Filter Realization via Deferred End-Around Carry Modular Addition
9VLSI18NXT09Modular Design of High-Efficiency Hardware Median Filter Architecture
10VLSI18NXT10An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture
11VLSI18NXT11Towards a Dependable True Random Number Generator With Self-Repair Capabilities
12VLSI18NXT12A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm
13VLSI18NXT13LFSR-Based Test Generation for Path Delay Faults
14VLSI18NXT14On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Scan Chains
15VLSI18NXT15DR-scan: Dual-rail Asynchronous Scan DfT and ATPG
16VLSI18NXT16On-Chip Diagnosis of Generalized Delay Failures using Compact Fault Dictionaries
17VLSI18NXT17Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs
18VLSI18NXT18Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks
19VLSI18NXT19Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring
20VLSI18NXT20An Adaptive Mechanism for Designing Efficient Snoop Filters
21VLSI18NXT21Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol equences
22VLSI18NXT22On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques
23VLSI18NXT23Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications
24VLSI18NXT24A Flexible and Energy-Efficient Convolutional Neural Network celebration With Dedicated ISA and Accelerator
25VLSI18NXT25Low-Cost Lifting Architecture and Lossless Implementation of Daubechies-8 Wavelets
26VLSI18NXT26A Method to Detect Bit Flips in a Soft-Error Resilient TCAM
27VLSI18NXT27Fault Group Pattern Matching with Efficient Early Termination for High-Speed Redundancy Analysis
28VLSI18NXT28Bitstream Fault Injections (BiFI) – Automated Fault Attacks against SRAM-based FPGAs
29VLSI18NXT29Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm.
30VLSI18NXT30Efficient Protection of the Register File in Soft-processors Implemented on Xilinx FPGAs