Combining thousands of transistors or devices into a single chip is called Very large scale integration. Nxtlogic is one of the leading software solution providers with a vision to develop corporate and academic projects with a precise approach on the student’s essential point and need, with the professional approach for problem identification, analysis and solving. We help you to develop your idea in VLSI using front end (Digital Design ) using HDL and Backend using CMOS Library dsign. This also covers the physical design and fault simulation. We help you in each and every process such as Problem specification, Architecture definition, Functional design, Logic design and Circuit design and Physical design and Packaging. We help you to work in languages such as Verilog , VHDL etc. We provide free training on the academic project topic you choose and make you to face viva with confidence. We provide full support for installing required frameworks and Software to run the project.We provide you free project training and full implementation explanation so that you can face viva with no fear. We help you with certain collection of latest IEEE-2017 Project titles. We assist you in paper publication in leading Journal.

S.NoProject CodeProject Title
VLSI Project Titles with Abstract
1VLSI17NXT01Content Addressable Memory—Early Predict and Terminate Prechargeof Match-Line
2VLSI17NXT02RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient
3VLSI17NXT03Design of Efficient BCD Adders in Quantum Dot
4VLSI17NXT04Efficient Designs of Multiported Memory on FPGA
5VLSI17NXT05Power-Gated 9T SRAM Cell for Low-Energy Operation
6VLSI17NXT06Efficient Designs of Multiported Memory on FPGA
7VLSI17NXT07Register Less Null Conversion Logic
8VLSI17NXT08Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
9VLSI17NXT09Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage
10VLSI17NXT10A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations
11VLSI17NXT11An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2k, 2P - 1}
12VLSI17NXT12Design of Power and Area Efficient Approximate Multipliers
13VLSI17NXT13Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
14VLSI17NXT14Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA
15VLSI17NXT15Test Stimulus Compression Based on Broadcast Scan with One Single Input
16VLSI17NXT16Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
17VLSI17NXT17Optimized Design of an LSSD Scan Cell
18VLSI17NXT18Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
19VLSI17NXT19A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes
20VLSI17NXT20An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA
21VLSI17NXT21Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching
22VLSI17NXT22High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
23VLSI17NXT24Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm
24VLSI17NXT25Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units
25VLSI17NXT26Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
26VLSI17NXT27Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology
27VLSI17NXT28Overloaded CDMA Crossbar for Network-On-Chip
28VLSI17NXT29Resource-Efficient SRAM-based Ternary Content Addressable Memory
29VLSI17NXT30Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
30VLSI17NXT31Selecting Replacements for Undetectable Path Delay Faults
31VLSI17NXT32Test Stimulus Compression Based on Broadcast Scan with One Single Input
32VLSI17NXT33A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs
33VLSI17NXT34A hybrid power amplifier using 3-phase 3-level class-D with 200nH inductors and current balancing technique
34VLSI17NXT35A 4GHz clock distribution architecture using subharmonically injection-locked coupled oscillators with clock skew calibration in 16nm CMOS