| S.No | Project Code | Validation-Details Project Topics | |
|---|---|---|---|
| VLSIProjects. | |||
| 1 | VLSI01 | AxPPA: Approximate Parallel Prefix Adders | |
| 2 | VLSI02 | Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors | |
| 3 | VLSI03 | An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths | |
| 4 | VLSI04 | Exact and Approximate Squarer’s for Error- Tolerant Applications | |
| 5 | VLSI05 | On the Design of Iterative Approximate Floating-Point Multipliers | |
| 6 | VLSI06 | Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization | |
| 7 | VLSI07 | A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators | |
| 8 | VLSI08 | Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders | |
| 9 | VLSI09 | Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM | |
| 10 | VLSI10 | Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM | |
| 11 | VLSI11 | Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer | |
| 12 | VLSI12 | Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS | |
| 13 | VLSI13 | High-Speed Counter With Novel LFSR State Extension | |
| 14 | VLSI14 | k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting | |
| 15 | VLSI15 | A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead | |
| 16 | VLSI16 | Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking | |
| 17 | VLSI17 | Efficient Error Detection for Matrix Multiplication With Systolic Arrays on FPGAs | |
| 18 | VLSI18 | FPGA-Based Configurable and Highly Flexible PAM4 SerDes Simulation System | |
| 19 | VLSI19 | STRAIT: Self-Test and Self-Recovery for AI Accelerator | |
| 20 | VLSI20 | Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests | |
| 21 | VLSI21 | Storage-Based Logic Built-In Self-Test With Cyclic Tests | |
| 22 | VLSI22 | Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults | |
| 23 | VLSI23 | Test Methodology for Defect-Based Bridge Faults | |
| 24 | VLSI24 | Path Unselection for Path Delay Fault Test Generation | |
| 25 | VLSI25 | A New Static Compaction of Deterministic Test Sets | |